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1364.1-2002 IEEE Standard for Verilog Register Transfer

Normal syntax and semantics for VerilogR HDL-based RTL synthesis are defined during this typical.

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Syntax NOTE—The subclauses within this clause are described using the same section hierarchy as described in the IEEE Std 1364-2001 LRM. This enables cross-referencing between the two standards to be much easier. 1 Lexical tokens Supported. 2 White space Supported. 3 Comments Supported. 4 Operators Supported. 5 Numbers number ::= decimal_number | octal_number | binary_number | hex_number | real_number real_number ::= unsigned_number . unsigned_number | unsigned_number [ . unsigned_number] exp [ sign ] unsigned_number exp ::= e | E decimal_number ::= unsigned_number | [ size ] decimal_base unsigned_number | [ size ] decimal_base x_digit { _ } | [ size ] decimal_base z_digit { _ } binary_number ::= [ size ] binary_base binary_value octal_number ::= [ size ] octal_base octal_value hex_number ::= [ size ] hex_base hex_value sign ::= + | size ::= non_zero_unsigned_number non_zero_unsigned_number ::= non_zero_decimal_digit { _ | decimal_digit } Copyright © 2002 IEEE.

The “value” is not defined by the standard. Examples of “value” are “cla” for +, “wallace” for *. Example 36: assign x = a + (* synthesis, implementation = "ripple" *) b; NOTE—The implementation is only a recommendation to the synthesis tool. 5 Keep attribute The syntax is: (* synthesis, keep [ = ] *) This attribute shall apply to a net, reg or a module instance or to a module. With the presence of this attribute on an instance or module, the instance or module shall be preserved, and not deleted nor replicated, even if the outputs of the module are not connected.

4 buif1, bufif0, notif1, and notif0 gates Supported. 44 Copyright © 2002 IEEE. All rights reserved. 5 MOS switches Not supported. 6 Bidirectional pass switches Not supported. 7 CMOS switches Not supported. 8 pullup and pulldown sources Not supported. 9 Logic strength modeling Ignored. 10 Strengths and values of combined signals Ignored. 11 Strength reduction by nonresistive devices Ignored. 12 Strength reduction by resistive devices Ignored. 13 Strengths of net types Ignored. 14 Gate and net delays Ignored.

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